Interrupt Status Enable Register
| TX_THLD_STS_EN | Transmit Buffer Threshold Status Enable |
| RX_THLD_STS_EN | Receive Buffer Threshold Status Enable |
| IBI_THLD_STS_EN | IBI Buffer Threshold Status Enable This bit is used only in Master mode of operation. |
| CMD_QUEUE_READY_STS_EN | Command Queue Ready Status Enable |
| RESP_READY_STS_EN | Response Queue Ready Status Enable |
| TRANSFER_ABORT_STS_EN | Transfer Abort Status Enable This bit is used only in Master mode of operation. |
| CCC_UPDATED_STS_EN | CCC Table Updated Status Enable This bit is used in Slave mode of operation. |
| DYN_ADDR_ASSGN_STS_EN | Dynamic Address Assigned Status Enable This bit is used in Slave mode of operation. |
| TRANSFER_ERR_STS_EN | Transfer Error Status Enable |
| DEFSLV_STS_EN | Define Slave CCC Received Status Enable |
| READ_REQ_RECV_STS_EN | Read Request Received Status Enable This bit is used in Slave mode of operation. |
| IBI_UPDATED_STS_EN | IBI Updated Status Enable This bit is used in Slave mode of operation. |
| BUSOWNER_UPDATED_STS_EN | Bus Owner Updated Status Enable |
| BUS_RESET_DONE_STS_EN | Bus Reset Pattern Generation Done Status Enable This bit is used only in Master mode of operation. |